— As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actua...
Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Dat...
—This paper introduces an accumulative prediction method to predict the eye diagram for high speed signaling systems. We use the step responses of pull-up and pull-down to extrac...
Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ern...
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
— Coupled oscillator networks occur in various domains such as biology, astrophysics and electronics. In this paper, we present a comprehensive procedure for rapid and accurate s...
— Perturbation Projection Vector (PPV) is an established technique for oscillator phase noise analysis; However, the PPV method significantly loses accuracy when circuits have l...