Test application time and volume compression through seed overlapping

We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architecture of the existing SCC scheme, while it attempts to overlap consecutive test vector seeds, thus providing increased flexibility in exploiting effectively the large volume of don’t-care bits in test vectors. We also introduce modified ATPG algorithms upon the previous SCC scheme and explore various implementation strategies. Experimental data exhibit significant reductions on test time and volume over all current test compression techniques. Categories and Subject Descriptors B.7.3 [Hardware]: Integrated Circuits—Reliability and Testing General Terms Design, Reliability, Verification, Algorithm Keywords Test Compression, SOC Test, Deterministic Test, XOR Network, Scan Chain Concealment

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
• Keywords: Computer Architecture, DAC 2003, Scan Chain Concealment, Test Compression, Test Time