TVLSI
2008
13 years 10 months ago
2008
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...
CORR
2008
Springer
13 years 11 months ago
2008
Springer
Online monitoring remains an important requirement for a range of microsystems. The solution based on the injection of an actuating test stimulus into the bias structure of active...
ETS
2010
IEEE
13 years 12 months ago
2010
IEEE
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
SDM
2010
SIAM
14 years 10 days ago
2010
SIAM
We present Confidence-based Feature Acquisition (CFA), a novel supervised learning method for acquiring missing feature values when there is missing data at both training and test...
DFT
2004
IEEE
14 years 2 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
ITC
1998
IEEE
14 years 3 months ago
1998
IEEE
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
DATE
2000
IEEE
14 years 3 months ago
2000
IEEE
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...
DAC
2003
ACM
14 years 4 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
ITC
2003
IEEE
14 years 4 months ago
2003
IEEE
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
DFT
2003
IEEE
14 years 4 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...