Test Generation for Global Delay Faults

This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the number of paths that must be tested. Results are given for the ISCAS85 benchmarks.

• Type: Conference
• Year: 1996
• Where: ITC
• Authors: G. M. Luong, D. M. H. Walker
• Keywords: Delay Faults, Global Process Disturbances, Hardware, ITC 1996, Paper Describes Test