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ICCAD
2002
IEEE

Test-model based hierarchical DFT synthesis

14 years 8 months ago
Test-model based hierarchical DFT synthesis
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution,
Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech,
Added 17 Mar 2010
Updated 17 Mar 2010
Type Conference
Year 2002
Where ICCAD
Authors Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng
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