Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

79

ASPDAC
2000
ACM

117views Hardware» more ASPDAC 2000»

A testability metric for path delay faults and its application

15 years 7 months ago

A testability metric for path delay faults and its application

Download cadlab.ece.ucsb.edu

Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agra

Real-time Traffic

ASPDAC 2000 | Hardware |

claim paper

Related Content

» On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set

» Deterministic Logic BIST for Transition Fault Testing

» A metric for routing in delaysensitive wireless sensor networks

» Variationdriven device sizing for minimum energy subthreshold circuits

» A LeastResistance Path in Reasoning about Unstructured Overlay Networks

» Resilient Overlay Networks

» POPI a userlevel tool for inferring router packet forwarding priority

» Hyperbolic embedding of internet graph for distance estimation and overlay construction

» Architecting protocol stack optimizations on mobile devices

Post Info
More Details (n/a)

Added	01 Aug 2010
Updated	01 Aug 2010
Type	Conference
Year	2000
Where	ASPDAC
Authors	Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal

Comments (0)