Thermal-aware task scheduling at the system software level

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System(OS) and existing hardware support. Categories and Subject Descriptors C.4 [PERFORMANCE OF SYSTEMS]: Design studies; Reliability, availability, and serviceability; D.4.1 [OPERATING SYSTEMS]: Process Management—Scheduling General Terms Reliability Keywords System Level Power Management, Thermal Management

• Type: Conference
• Year: 2007
• Where: ISLPED
• Authors: Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose
• Keywords: Current Generation Microprocessor, Hardware, ISLPED 2007, On-chip Temperatures, On-chip Unit Temperatures