Time Budgeting in a Wireplanning Context

Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented and buffered, their delay is linear in the path length and independent of the position of the modules along these paths. From timing requirements, the total budget left to modules after allocating the appropriate delay to the wires can be determined. This paper describes how this budget can be optimally divided amongst the modules. A novel, static timing-like, mathematical programming formulation is introduced such that the total module area is minimized. Instead of only the worst delay, all pin-to-pin delays are implicitly taken into account. If area-delay tradeoffs are convex, a reasonable approximation in practice, the program can be solved efficiently. Further, efficiency of different formulations is discussed, and a low-cost method of making the budget relatively immune to downstream uncertainties an...

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah
• Keywords: Appropriate Delay, DATE 2003, Hardware, Inputoutput Paths, Mathematical Programming Formulation