Time Domain Multiplexed TAM: Implementation and Comparison

One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are not directly accessible via chip inputs and outputs. In this paper we introduce a novel Test Access Mechanism (TAM) based on time domain multiplexing (TDM-TAM). This TAM is P1500 compatible and uses a P1500 wrapper. The TAM characteristics are its flexibility, scalability, and reconfigurability. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE1149.1 standard (Serial TAM)[7]and a packetswitching test network (NIMA)[9]. A network-processing engine SoC is used as a platform to compare the different TAMs [6]. Results show that in most cases, TDM is the most effective TAM in both test time and overhead area.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Zahra Sadat Ebadi, André Ivanov
• Keywords: DATE 2003, Hardware, TAM Characteristics, Test Access, Test Access Mechanism