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ICCAD
2009
IEEE

Timing Arc based logic analysis for false noise reduction

13 years 10 months ago
Timing Arc based logic analysis for false noise reduction
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
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