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    ICCAD
    2009
    IEEE
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    Timing Arc based logic analysis for false noise reduction
    13 years 9 months ago
    Timing Arc based logic analysis for false noise reduction
    Download  www.informatik.uni-bremen.de
    The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
    Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
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