Timing-driven variation-aware nonuniform clock mesh synthesis

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maxi...

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
• Keywords: Clock Skew, Clock Skew Variations, GLVLSI 2010, Skew Variations, VLSI