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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
14 years 16 days ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
14 years 1 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
14 years 4 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...