Towards layout-friendly high-level synthesis

There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis has been proposed to solve the complexity problem by raisabstraction level. In this paper, we share our vision that high-level synthesis can potentially help the routability problem as well. We show that many interconnect problems that occur in layout can be avoided or mitigated by adopting a layout-friendly RTL architecture generated from highlevel synthesis. We also evaluate some structural metrics that can be used to estimate the routability impact of design decisions in high-level synthesis. Experimental results have demonstrated correlations between the metrics and the routability of the resulting design. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids—automatic synthesis, optimization; G.3 [Mathematics of Computing]: Probability and Statistics—correlation and regression analysis G...

• Type: Journal
• Year: 2012
• Where: ISPD
• Authors: Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabhakar
• Keywords: Automatic Synthesis, Hardware, ISPD 2012, Level Synthesis, Statistics Correlation