Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlevel power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by onchip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive parasitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. W...

• Type: Journal
• Year: 2010
• Where: DAC
• Authors: Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li
• Keywords: Computer Architecture, DAC 2010, On-chip Voltage, Power Delivery, Voltage Droop