Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology

Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high Vt sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as Vdd, Vt, and sleep transistor sizing.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: James Kao, Anantha Chandrakasan, Dimitri Antoniadis
• Keywords: Computer Architecture, DAC 1997, Sizing, Sleep Transistor, Vt Sleep Transistor