OR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract With potential application to a variety of industries, fleet sizing problems present a prevalent and significant challenge for engineers and managers. This is especially t...
JCO
2011
13 years 6 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
TCAD
1998
13 years 10 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
TCAD
2008
13 years 11 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
SIGMETRICS
2008
ACM
13 years 11 months ago
2008
ACM
In this paper, we discuss recent work on buffer sizing in the context of an ISP's need to offer and guarantee competitive Service Level Agreements (SLAs) to its customers. Si...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
ICCAD
2007
IEEE
14 years 3 months ago
2007
IEEE
DAC
2010
ACM
14 years 3 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
DAC
1997
ACM
14 years 3 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...