TSV stress aware timing analysis with applications to 3D-IC layout optimization

As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile stress on silicon near TSV. In this paper, we propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, we generate a stress contour map with an analytical radial stress model. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relation between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. It is interesting to observe that rise and fall time react differently to st...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan
• Keywords: Computer Architecture, DAC 2010, Timing Analysis, TSV Stress, TSV fill Material