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    DAC
    2010
    ACM
    164views Computer Architecture» more  DAC 2010»
    TSV stress aware timing analysis with applications to 3D-IC layout optimization
    14 years 3 months ago
    TSV stress aware timing analysis with applications to 3D-IC layout optimization
    Download  www.gtcad.gatech.edu
    As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
    Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
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