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127
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DAC
2010
ACM
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Computer Architecture
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DAC 2010
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TSV stress aware timing analysis with applications to 3D-IC layout optimization
15 years 7 months ago
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www.gtcad.gatech.edu
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
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