The VHDL based design of the MIDA MPEG1 audio decoder

This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL descriptions, and has been implemented using a cell based approach and a 0.7 µm, 2 metal layers CMOS technology. The die area is 95 mm2. Synthesis tools have also been used for automatic insertion of test structures and automatic test pattern generation.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Andrea Finotello, Maurizio Paolini
• Keywords: Automatic Synthesis, Automatic Test Pattern Generation, EURODAC 1995, Metal Layers Cmos, VHDL