Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

93

Voted

SASP
2009
IEEE

146views Hardware» more SASP 2009»

Workload adaptive shared memory multicore processors with reconfigurable interconnects

15 years 9 months ago

Workload adaptive shared memory multicore processors with reconfigurable interconnects

Download www.icims.csl.uiuc.edu

Shoaib Akram, Rakesh Kumar, Deming Chen

Real-time Traffic

Hardware | SASP 2009 |

claim paper

Related Content

» Online cache modeling for commodity multicore processors

» A dynamically reconfigurable cache for multithreaded processors

» A study of the onchip interconnection network for the IBM Cyclops64 multicore architecture

» Erasing Core Boundaries for Robust and Configurable Performance

» The multikernel a new OS architecture for scalable multicore systems

» Improving SMT performance an application of genetic algorithms to configure resizable cach...

Post Info
More Details (n/a)

Added	21 May 2010
Updated	21 May 2010
Type	Conference
Year	2009
Where	SASP
Authors	Shoaib Akram, Rakesh Kumar, Deming Chen

Comments (0)