Sciweavers

ISPD
2004
ACM
189views Hardware» more  ISPD 2004»
14 years 3 months ago
Almost optimum placement legalization by minimum cost flow and dynamic programming
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
Ulrich Brenner, Anna Pauli, Jens Vygen
ISPD
2004
ACM
171views Hardware» more  ISPD 2004»
14 years 3 months ago
Structured ASIC, evolution or revolution?
This paper describes the structured ASIC technology and impacts to the implementation flow. With an optimized and programmable structure, the structured ASIC technology indeed int...
Kun-Cheng Wu, Yu-Wen Tsai
ISPD
2004
ACM
161views Hardware» more  ISPD 2004»
14 years 3 months ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
ISPD
2004
ACM
150views Hardware» more  ISPD 2004»
14 years 3 months ago
Topology optimization of structured power/ground networks
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
Jaskirat Singh, Sachin S. Sapatnekar
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 3 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
Hardware
Top of PageReset Settings