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DFT
2004
IEEE
134views VLSI» more  DFT 2004»
14 years 1 months ago
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density comp...
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lomb...
DFT
2004
IEEE
174views VLSI» more  DFT 2004»
14 years 1 months ago
Defect Avoidance in a 3-D Heterogeneous Sensor
A 3D Heterogeneous Sensor using a stacked chip is investigated. Optical Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned col...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
14 years 1 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DFT
2004
IEEE
118views VLSI» more  DFT 2004»
14 years 1 months ago
Defect Characterization for Scaling of QCA Devices
Quantum dot Cellular Automata (QCA) is amongst promising new computing scheme in the nano-scale regimes. As an emerging technology, QCA relies on radically different operations in...
Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tah...
DFT
2004
IEEE
102views VLSI» more  DFT 2004»
14 years 1 months ago
Exploiting an I-IP for In-Field SOC Test
Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza ...
VLSI
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