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» *T: A Multithreaded Massively Parallel Architecture
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EUROPAR
2009
Springer
14 years 2 months ago
High Performance Matrix Multiplication on Many Cores
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zha...
SBACPAD
2008
IEEE
127views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Measuring Operating System Overhead on CMT Processors
Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies exami...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
IPPS
2008
IEEE
14 years 2 months ago
Qthreads: An API for programming with millions of lightweight threads
Large scale hardware-supported multithreading, an attractive means of increasing computational power, benefits significantly from low per-thread costs. Hardware support for ligh...
Kyle B. Wheeler, Richard C. Murphy, Douglas Thain
CASES
2003
ACM
14 years 26 days ago
Architectural optimizations for low-power, real-time speech recognition
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
TPDS
1998
107views more  TPDS 1998»
13 years 7 months ago
A Practical Approach to Dynamic Load Balancing
—This paper presents a cohesive, practical load balancing framework that improves upon existing strategies. These techniques are portable to a broad range of prevalent architectu...
Jerrell Watts, Stephen Taylor