36 search results - page 6 / 8 » 3D FFT for FPGAs |
168
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ISMVL
1998
IEEE
15 years 10 months ago
1998
IEEE
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...
174
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ASAP
2008
IEEE
16 years 19 days ago
2008
IEEE
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
146
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IPPS
1997
IEEE
15 years 10 months ago
1997
IEEE
An analysis is presented of the primary factors influencing the performance of a parallel implementation of the UCLA atmospheric general circulation model (AGCM) on distributedme...
206
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ARC
2012
Springer
14 years 1 months ago
2012
Springer
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
160
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ISAAC
2003
Springer
15 years 11 months ago
2003
Springer
Abstract. Fast algorithms for arithmetic on real or complex polynomials are wellknown and have proven to be not only asymptotically efficient but also very practical. Based on Fas...