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ISMVL
1998
IEEE

Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic

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Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode techniques, reducing the transistor count to half compared to that of a binary implementation. Two main applications for multiple-valued LUTs are multiple-valued FPGAs and intelligent memories. An FPGA uses a LUT as a generic logic block to provide programmability. In an intelligent memory, a multiplevalued LUT is added in the Y-decoder section to facilitate simple mathematical operations on the stored digits. An FFT operation is used as an example in this paper to illustrate how a multiple-valued LUT can be beneficial.
Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISMVL
Authors Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
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