Scalable Memory Hierarchies for Embedded Manycore Systems

As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typical embedded systems in which both data and instructions are stored in the off-chip global memory will introduce the bus contention problem as the number of processing cores increases. In this work, we present our exploration into how distributed multi-tiered memory hierarchies can effect the scalability of manycore systems. We use the Xilinx Virtex FPGA devices as the testing platforms and the buses as the interconnect. Several variances of the centralized memory hierarchy and the distributed memory hierarchy are compared by running various benchmarks, including matrix multiplication, IDEA encryption and 3D FFT. The results demonstrate the good scalability of the distributed memory hierarchy for systems up to 32 MicroBlaze processors, which is constrained by the FPGA resources on the Virtex-6LX240T device.

• Type: Journal
• Year: 2012
• Where: ARC
• Authors: Sen Ma, Miaoqing Huang, Eugene Cartwright, David L. Andrews
• Keywords: ARC 2012, Hardware, Memory Hierarchies, Memory Hierarchy, Xilinx Virtex