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» A 3d-audio reconfigurable processor
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ERSA
2004
106views Hardware» more  ERSA 2004»
13 years 10 months ago
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms
Advanced multimedia applications (e.g. based on MPEG-4) will consist of multiple scalable multimedia objects. This scalability enables the application to adapt to different proces...
Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignole...
IPPS
2007
IEEE
14 years 3 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
DSD
2009
IEEE
105views Hardware» more  DSD 2009»
14 years 3 months ago
Design of a Highly Dependable Beamforming Chip
—As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip 1 is designe...
Xiao Zhang, Hans G. Kerkhoff
HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
FPL
2010
Springer
111views Hardware» more  FPL 2010»
13 years 7 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...