13 search results - page 1 / 3 » A Bit-Node Centric Architecture for Low-Density Parity-Check... |
GLOBECOM
2007
IEEE
14 years 5 months ago
2007
IEEE
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
ICCCN
2007
IEEE
14 years 5 months ago
2007
IEEE
—A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to c...
ASAP
2006
IEEE
14 years 2 months ago
2006
IEEE
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
GLOBECOM
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
ICASSP
2008
IEEE
14 years 5 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...