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CGO
2004
IEEE
13 years 11 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
DSD
2009
IEEE
105views Hardware» more  DSD 2009»
14 years 2 months ago
Design of a Highly Dependable Beamforming Chip
—As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip 1 is designe...
Xiao Zhang, Hans G. Kerkhoff
ICPP
1999
IEEE
13 years 11 months ago
Parallel Media Processors for the Billion-Transistor Era
This paper describes the challenges presented by singlechip parallel media processors (PMPs). These machines integrate multiple parallel function units, instruction execution, and...
Jason Fritts, Zhao Wu, Wayne Wolf
ICFP
2010
ACM
13 years 7 months ago
ReCaml: execution state as the cornerstone of reconfigurations
Most current techniques fail to achieve the dynamic update of recursive functions. A focus on execution states appears to be essential in order to implement dynamic update in this...
Jérémy Buisson, Fabien Dagnat
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
14 years 24 days ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling