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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
CPE
1998
Springer
81views Hardware» more  CPE 1998»
15 years 8 months ago
Experiments with Improved Approximate Mean Value Analysis Algorithms
Abstract. Approximate Mean Value Analysis (MVA) is a popular technique for analyzing queueing networks because of the efficiency and accuracy that it affords. In this paper, we pre...
Hai Wang, Kenneth C. Sevcik
ACSC
2004
IEEE
15 years 8 months ago
Exploiting FPGA Concurrency to Enhance JVM Performance
The Java Programming Language has been praised for its platform independence and portability, but because of its slow execution speed on a software Java Virtual Machine (JVM), som...
James Parnis, Gareth Lee
SIGMETRICS
2008
ACM
116views Hardware» more  SIGMETRICS 2008»
15 years 4 months ago
Towards realistic file-system benchmarks with CodeMRI
Benchmarks are crucial to understanding software systems and assessing their performance. In file-system research, synthetic benchmarks are accepted and widely used as substitutes...
Nitin Agrawal, Andrea C. Arpaci-Dusseau, Remzi H. ...
DATE
2011
IEEE
235views Hardware» more  DATE 2011»
14 years 8 months ago
An Overview of Approaches Towards the Timing Analysability of Parallel Architecture
In order to meet performance/low energy/integration requirements, parallel architectures (multithreaded cores and multi-cores) are more and more considered in the design of embedd...
Christine Rochange