65 search results - page 7 / 13 » A Cache Consistency Protocol for Multiprocessors with Multis... |
CDES
2008
13 years 9 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
ICS
1998
Tsinghua U.
13 years 11 months ago
1998
Tsinghua U.
In this paper we propose the OPTNET, a novel optical network and associated coherence protocol for scalable multiprocessors. The network divides its channels into broadcast and po...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network. Control messages are forwarded using the ring...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
WDAG
2005
Springer
14 years 29 days ago
2005
Springer
Transactional Memory is a concurrent programming API in which concurrent threads synchronize via transactions (instead of locks). Although this model has mostly been studied in the...