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» A Caching Strategy to Improve iSCSI Performance
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JEC
2006
107views more  JEC 2006»
13 years 7 months ago
A dynamically reconfigurable cache for multithreaded processors
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance...
Alex Settle, Dan Connors, Enric Gibert, Antonio Go...
ICPP
2009
IEEE
13 years 5 months ago
Cache-Efficient, Intranode, Large-Message MPI Communication with MPICH2-Nemesis
The emergence of multicore processors raises the need to efficiently transfer large amounts of data between local processes. MPICH2 is a highly portable MPI implementation whose l...
Darius Buntinas, Brice Goglin, David Goodell, Guil...
ASPLOS
1994
ACM
13 years 11 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
PSTV
1992
113views Hardware» more  PSTV 1992»
13 years 8 months ago
Coverage Preserving Reduction Strategies for Reachability Analysis
We study the effect of three new reduction strategies for conventional reachability analysis, as used in automated protocol validation algorithms. The first two strategies are imp...
Gerard J. Holzmann, Patrice Godefroid, Didier Piro...
LCPC
2009
Springer
14 years 6 days ago
A Balanced Approach to Application Performance Tuning
Abstract. Current hardware trends place increasing pressure on programmers and tools to optimize scientific code. Numerous tools and techniques exist, but no single tool is a pana...
Souad Koliai, Stéphane Zuckerman, Emmanuel ...