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IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 6 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
DATE
2008
IEEE
167views Hardware» more  DATE 2008»
14 years 3 months ago
Accuracy-Adaptive Simulation of Transaction Level Models
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
Martin Radetzki, Rauf Salimi Khaligh
WMPI
2004
ACM
14 years 2 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
14 years 24 days ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
AC
1999
Springer
14 years 29 days ago
The University Student Registration System: A Case Study in Building a High-Availability Distributed Application Using General P
Prior to 1994, student registration at Newcastle University involved students being registered in a single place, where they would present a form which had previously been filled ...
Mark C. Little, Stuart M. Wheater, David B. Ingham...