334 search results - page 31 / 67 » A Case for Deconstructing Hardware Transactional Memory Syst... |
ICPP
2009
IEEE
13 years 6 months ago
2009
IEEE
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
-- One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemente...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
PARCO
2003
13 years 10 months ago
2003
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...