334 search results - page 42 / 67 » A Case for Deconstructing Hardware Transactional Memory Syst... |
ASAP
2005
IEEE
14 years 2 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
DSD
2006
IEEE
14 years 2 months ago
2006
IEEE
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis...
ICECCS
2007
IEEE
14 years 14 days ago
2007
IEEE
Parts of the CICS transaction processing system were modelled formally in the 1980s in a collaborative project between IBM Hursley Park and Oxford University Computing Laboratory....
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...