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» A Characterization of Constructive Dimension
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134
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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
16 years 1 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
148
Voted
SEMCO
2009
IEEE
15 years 11 months ago
Enhanced Multimedia Content Access and Exploitation Using Semantic Speech Retrieval
—Techniques for automatic annotation of spoken content making use of speech recognition technology have long been characterized as holding unrealized promise to provide access to...
Roeland Ordelman, Franciska de Jong, Martha Larson
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
15 years 11 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng
FOSSACS
2010
Springer
15 years 11 months ago
On the Relationship between Spatial Logics and Behavioral Simulations
Abstract. Spatial logics have been introduced to reason about distributed computation in models for concurrency. We first define a spatial logic for a general class of infinite-...
Lucia Acciai, Michele Boreale, Gianluigi Zavattaro
ICDCSW
2008
IEEE
15 years 11 months ago
RETROFIT: Reliable Exchanges through Resilient Overlays for Internet Teleoperation
Emergence of successful teleoperation applications requires the convergence of diverse domains like robotics, machine learning, sensing, actuation, control and communication. We e...
Invited Talk Lakshamanan, Raj Rajkumar