The systolic array paradigm has low communication demand because it does not use costly global communication and each processor communicates with few other processors. It is thus s...
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishr...
Code generation for embedded processors creates opportunities for several performance optimizations not applicable for traditional compilers. We present techniques for improving d...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
Marcel-Catalin Rosu, Karsten Schwan, Richard Fujim...
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...