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» A Clustered Approach to Multithreaded Processors
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ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
SC
2009
ACM
14 years 2 months ago
Scalable computing with parallel tasks
Recent and future parallel clusters and supercomputers use SMPs and multi-core processors as basic nodes, providing a huge amount of parallel resources. These systems often have h...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
KDD
2005
ACM
124views Data Mining» more  KDD 2005»
14 years 8 months ago
A multinomial clustering model for fast simulation of computer architecture designs
Computer architects utilize simulation tools to evaluate the merits of a new design feature. The time needed to adequately evaluate the tradeoffs associated with adding any new fe...
Kaushal Sanghai, Ting Su, Jennifer G. Dy, David R....
CGO
2004
IEEE
13 years 11 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
CLUSTER
2006
IEEE
13 years 11 months ago
Lightweight I/O for Scientific Applications
Today's high-end massively parallel processing (MPP) machines have thousands to tens of thousands of processors, with next-generation systems planned to have in excess of one...
Ron Oldfield, Lee Ward, Rolf Riesen, Arthur B. Mac...