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ASPLOS
2010
ACM
13 years 10 months ago
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantl...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
COMPUTER
2006
84views more  COMPUTER 2006»
13 years 7 months ago
Testable, Reusable Units of Cognition
The educational content of a technical topic consists, ultimately, of elementary chunks of knowledge. Identifying and classifying such units -- Testable, Reusable Units of Cogniti...
Bertrand Meyer
BMCBI
2010
145views more  BMCBI 2010»
13 years 2 months ago
Directionality in protein fold prediction
Background: Ever since the ground-breaking work of Anfinsen et al. in which a denatured protein was found to refold to its native state, it has been frequently stated by the prote...
Jonathan J. Ellis, Fabien P. E. Huard, Charlotte M...
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
14 years 1 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...
LCTRTS
2007
Springer
14 years 1 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...