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ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
14 years 3 months ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
CODES
2005
IEEE
14 years 3 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
GCC
2006
Springer
14 years 1 months ago
Redar: A Remote Desktop Architecture for the Distributed Virtual Personal Computing
Some popular computing technologies, such as ubiquitous computing, grid computing and thin-client computing, bring people to a much more distributed and pervasive computing enviro...
Yuedong Zhang, Zhenhua Song, Dingju Zhu, Zhuan Che...
ISPASS
2006
IEEE
14 years 4 months ago
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures
The present work presents a cycle-level execution-driven simulator for modern GPU architectures. We discuss the simulation model used for our GPU simulator, based in the concept o...
Victor Moya Del Barrio, Carlos González, Jo...
SIMUTOOLS
2008
13 years 11 months ago
Simulating SMEPP middleware
Embedded Peer-to-Peer Systems (EP2P) represent a new challenge in the development of software for distributed systems. The main objective of the SMEPP (Secure Middleware for Embed...
Javier Barbarán, Carlos Bonilla, Jose &Aacu...