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DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 1 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 1 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
IPPS
2007
IEEE
14 years 1 months ago
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas A...
BMCBI
2010
153views more  BMCBI 2010»
13 years 7 months ago
Pash 3.0: A versatile software package for read mapping and integrative analysis of genomic and epigenomic variation using massi
Background: Massively parallel sequencing readouts of epigenomic assays are enabling integrative genome-wide analyses of genomic and epigenomic variation. Pash 3.0 performs sequen...
Cristian Coarfa, Fuli Yu, Christopher A. Miller, Z...