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» A Container-Iterator Parallel Programming Model
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PDP
2005
IEEE
14 years 2 months ago
A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol
SVM systems are a cheaper and flexible way to implement the shared memory programming paradigm. Their huge flexibility is due to their software implementation; however, this is al...
Salvador Petit, Julio Sahuquillo, Ana Pont
EDO
2005
Springer
14 years 2 months ago
Optimizing layered middleware
Middleware is often built using a layered architectural style. Layered design provides good separation of the diļ¬€erent concerns of middleware, such as communication, marshaling, ...
Ömer Erdem Demir, Premkumar T. Devanbu, Eric ...
IPPS
2003
IEEE
14 years 2 months ago
Performance and Overhead in a Hybrid Reconfigurable Computer
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelĀ...
Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
CONCUR
2000
Springer
14 years 1 months ago
LP Deadlock Checking Using Partial Order Dependencies
Model checking based on the causal partial order semantics of Petri nets is an approach widely applied to cope with the state space explosion problem. One of the ways to exploit su...
Victor Khomenko, Maciej Koutny
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 22 days ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...