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» A Decimal Floating-Point Specification
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FPL
2007
Springer
127views Hardware» more  FPL 2007»
14 years 1 months ago
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wa...
CJ
2010
80views more  CJ 2010»
13 years 7 months ago
Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
Behzad Akbarpour, Amr T. Abdel-Hamid, Sofiè...
ERSA
2006
129views Hardware» more  ERSA 2006»
13 years 9 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
ICCD
2007
IEEE
151views Hardware» more  ICCD 2007»
14 years 4 months ago
Benchmarks and performance analysis of decimal floating-point applications
The IEEE P754 Draft Standard for Floating-point Arithmetic provides specifications for Decimal Floating-Point (DFP) formats and operations. Based on this standard, many developer...
Liang-Kai Wang, Charles Tsen, Michael J. Schulte, ...
CIT
2006
Springer
13 years 11 months ago
Design of Novel Reversible Carry Look-Ahead BCD Subtractor
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
Himanshu Thapliyal, Sumedha K. Gupta