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» A Decompression Architecture for Low Power Embedded Systems
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TECS
2008
122views more  TECS 2008»
13 years 7 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
EMSOFT
2007
Springer
14 years 1 months ago
Slice-balancing H.264 video encoding for improved scalability of multicore decoding
With multicore architectures being introduced to the market, the research community is revisiting problems to evaluate them under the new preconditions set by those new systems. A...
Michael Roitzsch
DPD
2006
98views more  DPD 2006»
13 years 7 months ago
GRACE-based joins on active storage devices
Contemporary long-term storage devices feature powerful embedded processors and sizeable memory buffers. Active Storage Devices (ASD) is the hard disk technology that makes use of ...
Vassilis Stoumpos, Alex Delis
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
13 years 7 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 2 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova