Sciweavers

714 search results - page 15 / 143
» A Decompression Architecture for Low Power Embedded Systems
Sort
View
CSREAESA
2007
15 years 5 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
16 years 5 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
148
Voted
MOBIHOC
2000
ACM
15 years 8 months ago
Low power rendezvous in embedded wireless networks
ln the future, wireless networking will be embedded into a wide variety of common, everyday objects [1]. In many embedded networking situations, the communicating nodes will be ver...
Terry Todd, Frazer Bennett, Alan Jones
ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
15 years 10 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 10 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...