Sciweavers

714 search results - page 16 / 143
» A Decompression Architecture for Low Power Embedded Systems
Sort
View
TVLSI
2010
13 years 3 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
IPPS
1998
IEEE
14 years 29 days ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
EUC
2005
Springer
14 years 2 months ago
On Tools for Modeling High-Performance Embedded Systems
Abstract. Most of the new embedded systems require high performance processors at low power. To cater to these needs, most semiconductor companies are designing multi-core processo...
Anilkumar Nambiar, Vipin Chaudhary
SAMOS
2004
Springer
14 years 2 months ago
A Low-Power Multithreaded Processor for Baseband Communication Systems
Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low inter...
Michael J. Schulte, C. John Glossner, Suman Mamidi...
CODES
2004
IEEE
14 years 13 days ago
Low energy security optimization in embedded cryptographic systems
Future embedded and wireless devices will be increasingly powerful supporting many applications including one of the most crucial, security. Although many wireless and embedded de...
Catherine H. Gebotys