714 search results - page 20 / 143 » A Decompression Architecture for Low Power Embedded Systems |
VLSID
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes the system design of a lowpower wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties...
ASPDAC
2007
ACM
14 years 21 days ago
2007
ACM
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
DAC
1995
ACM
14 years 8 days ago
1995
ACM
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
HIPEAC
2009
Springer
14 years 3 months ago
2009
Springer
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...