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» A Decompression Architecture for Low Power Embedded Systems
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CASES
2004
ACM
14 years 28 days ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
APCSAC
2006
IEEE
14 years 1 months ago
Power-Efficient Microkernel of Embedded Operating System on Chip
Because the absence of hardware support, almost all of embedded operating system are based on SDRAM in past time. With progress of embedded system hardware, embedded system can pro...
Tianzhou Chen, Wei Hu, Yi Lian
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 1 months ago
Very wide register: an asymmetric register file organization for low power embedded processors
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
GLVLSI
2008
IEEE
169views VLSI» more  GLVLSI 2008»
13 years 7 months ago
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
ISCAPDCS
2008
13 years 9 months ago
Parallel Embedded Systems: Where Real-Time and Low-Power Meet
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
Zdravko Karakehayov, Yu Guo