59 search results - page 10 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
INFOCOM
2006
IEEE
14 years 1 months ago
2006
IEEE
— The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high line speeds. A central problem in designing an input-queued swit...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
ISSS
2002
IEEE
14 years 1 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...